The present invention relates to a method of manufacturing a germanium-on-insulator substrate.
For the last few decades, rigorous scaling methods have been driving the silicon (Si) complementary metal-oxide-semiconductor (CMOS) technology to enhance device performance, lower the associated power consumption required, and reduce manufacturing costs per transistor. As device dimension shrinks and progresses to closer to the scaling limit, a paradigm shift has occurred in the industry from focusing only on dimensional scaling alone to actively exploring materials innovation (“performance boosters”). One such example is the III-V compound materials due to their unique properties for potential future high speed and low power computation applications. Compared to Si, III-V materials tend to display 20-70 times higher electron mobility and approximately 20 times higher conductivity. In addition, the feasibility of energy bandgap engineering of III-V materials enables fabrication of devices suitable for communications and optoelectronics. However, III-V materials cannot completely replace Si because III-V substrates are very costly and smaller in size due to their brittle materials properties (usually smaller or equal to 200 mm). Therefore, to get around the problem, small quantity of III-V materials has to be integrated with Si substrates to be compatible with mainstream CMOS manufacturing. In order to realize III-V materials integration on low cost and provide mechanically strong Si substrates, a number of research groups have investigated III-V growth on Si for optoelectronics and microelectronics applications.
One challenge in producing high quality III-V materials on Si suitable for manufacturing compatibility with existing CMOS technology is the large lattice mismatch between the two materials (e.g. in the case of GaAs, the mismatch is about 4.1%). So to resolve the problem, germanium (Ge), which has a lattice constant that is almost perfectly matched to GaAs (0.07% mismatch at 300 K) and has superior electron and hole mobility compared to Si, may be grown on Si to provide a buffer layer for integration and fabrication of GaAs based devices on Si substrate. Another possible solution is to form Germanium-on-Insulator (GOI) substrate for the same application above. Besides acting as a “passive” buffer layer, Ge on Si or GOI substrates (with no III-V layers) also have applications in advanced CMOS circuit and photonics.
Conventional solutions have reported on high quality of Ge epitaxial layer grown on Si with threading dislocation density (TDD) of approximately 105 cm−2 but it however requires growing a thick (about 10 μm) graded SiGe buffer layer. Another approach is to deposit Ge directly on a Si substrate and then introduce an annealing step during and after the Ge growth to reduce TDD. The techniques involve using a two-step low temperature/high temperature (LT/HT) Ge growth and also via other combinations. However, these methods result in a much higher TDD of greater than 107 cm−2. In particular, the high TDD level may degrade any subsequent III-V materials integration, and may also further undesirably lead to device failure.
One object of the present invention is therefore to address at least one of the problems of the prior art and/or to provide a choice that is useful in the art.